1. Field of the Invention
Example embodiments of the present invention relate to a method of manufacturing a semiconductor device. More particularly, example embodiment of the present invention relate to a method of manufacturing a complementary metal-oxide semiconductor (CMOS) device having a dual gate structure.
2. Description of the Related Art
A metal-oxide semiconductor (MOS) transistor is classified as either an N-type MOS (NMOS) transistor or a P-type MOS (PMOS) transistor according to a kind of a channel. When both the NMOS transistor and the PMOS transistor are formed in a semiconductor substrate to form a transistor, the transistor is called a complementary MOS (CMOS).
Up to now, polysilicon has been typically used as a gate electrode of a CMOS transistor, and the polysilicon gate electrode of the CMOS is commonly doped with P-type impurities or N-type impurities in accordance with an electrical polarity of impurities doped into source/drain regions of the substrate. As a semiconductor device becomes more highly integrated, however, there are many problems that arise in using polysilicon as the gate electrode of the CMOS transistor.
A polysilicon gate needs to be heavily doped with impurities in order to have conductivity similar to that of metal, and dopant solubility in the polysilicon gate is limited to about 5×1020 atoms/cm3. Because the dopant solubility restricts a number of electron carriers in the polysilicon gate, when a voltage is applied to the gate electrode a depletion layer is formed at an interface between the polysilicon gate and a gate dielectric layer formed below the polysilicon gate. The depletion layer in the polysilicon gate increases an equivalent oxide thickness (EOT) of a transistor by at least about 4 to about 5 Å so that the depletion layer acts as a factor in reducing a driving current of the transistor.
A silicon oxide layer or a silicon oxynitride layer has been mainly used as the gate dielectric layer, which has physical limitations in improving electrical characteristics as a thickness of the gate dielectric layer is reduced. That is, reliability of the gate dielectric layer is reduced as the gate dielectric layer becomes thinner and thinner. For example, when the thickness of a silicon oxide gate dielectric layer is reduced to no more than about 20 Å, a leakage current at a gate electrode increases by a direct tunneling, and power consumption also increases. Thus, there are limitations in reducing the thickness of the gate dielectric layer when the gate dielectric layer includes silicon oxide or silicon oxynitride.
In order to overcome the above-mentioned problems, research has been recently conducted on a gate dielectric layer including a material having a high dielectric constant (i.e., a “high-k” gate dielectric layer) in place of the silicon oxide or silicon oxynitride, because the high-k gate dielectric layer can be formed to a relatively small EOT and can sufficiently reduce the leakage current between the gate electrode and a channel region.
However, when the gate dielectric layer includes a high-k material and the gate electrode includes polysilicon in a MOS transistor, problems can result. For instance, defect states and a plurality of bulk traps at an interface between the semiconductor substrate and the gate dielectric layer capture conducting electrons so that a Fermi level is pinned at a charge neutrality level or at a central portion of an energy band positioned near the charge neutrality level. Hence, a problem occurs in that a threshold voltage (Vth) greatly increases.
A depletion effect and a pinning phenomenon of the Fermi level of the polysilicon gate electrode occur more seriously in the PMOS transistor. Particularly, in a case of the PMOS transistor, dopants, i.e., boron (B), penetrate a gate insulation layer and permeate a channel region of the semiconductor substrate to change a flat-band voltage (Vfb) and the threshold voltage (Vth), and degenerate reliability of elements.
For the above reasons, there is a strong tendency for polysilicon to be substituted with a metallic material for a gate electrode. The metallic material has an extremely large number of carriers (about 5×1022 atoms/cm3) so that a thickness of the depletion region becomes substantially zero. Thus, when the gate electrode includes metal in place of polysilicon, the depletion effect and the pinning phenomenon of the Fermi level can be sufficiently prevented. However, the metallic material has a disadvantage of thermal instability as compared to polysilicon, and the processing steps for forming the metallic gate electrode is incompatible with existing processing steps for forming the polysilicon gate electrode.
Thus, a metal/polysilicon gate stack structure in which a metallic gate is interposed between the gate dielectric layer and the polysilicon gate are proposed. According to the metal/polysilicon gate stack structure, the depletion effect of polysilicon can be removed and the pinning phenomenon of the Fermi level can be prevented, while compatibility with the existing process is still maintained.
A work function of the metallic gate determines a doping level of the semiconductor substrate and the threshold voltage of the MOS transistor. Thus, in a CMOS transistor, where both the NMOS transistor and the PMOS transistor require a low threshold voltage of about 0.3 to about 0.6 V, a material included in the metallic gate requires a work function of about 4.0 to about 4.4 eV in the NMOS transistor, and a work function of about 4.8 to about 5.2 eV in the PMOS transistor.
FIGS. 1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual gate structure according to one conventional method.
Referring to FIG. 1A, a gate dielectric layer 12 is formed on a semiconductor substrate 10 having a PMOS transistor area and an NMOS transistor area. After forming a first metal layer 14 on the gate dielectric layer 12, the first metal layer 14 formed in the NMOS transistor area is selectively removed so that only the first metal layer 14 formed in the PMOS transistor area remains.
Referring to FIG. 1B, a second metal layer 16 is formed on the first metal layer 14 and the gate dielectric layer 12. Thus, a first metal gate including the first metal layer 14 and the second metal layer 16 is formed on the PMOS transistor area, and a second metal gate including the second metal layer 16 is formed in the NMOS transistor area.
According to the above-mentioned conventional method, a work function of a gate electrode of the PMOS transistor primarily depends upon the first metal layer 14, and a work function of a gate electrode of the NMOS transistor primarily depends upon the second metal layer 16. Thus, a dual gate electrode having a work function required for each of the PMOS transistor and the NMOS transistor can be formed.
However, according to the above-mentioned conventional method, when the first metal layer 14 in the NMOS transistor area is removed, the gate dielectric layer 12 is exposed to an etching chemical, so that the gate dielectric layer may be damaged by etching. Thus, dielectric characteristics of the gate dielectric layer 12 are degraded.
FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device having a dual gate structure according to another conventional method.
Referring to FIG. 2, after forming a gate dielectric layer 52 on a semiconductor substrate 50 having a PMOS transistor area and an NMOS transistor area, a metal layer 54 is thickly formed on the gate dielectric layer 52. Sequentially, the metal layer 54 formed in the NMOS transistor area is etched with a predetermined thickness by a timed etching process so that a thin metal layer 54a with a desired thickness remains in the NMOS transistor area.
According to the above conventional method, a work function of a gate electrode of the PMOS transistor primarily depends upon the thick metal layer 54, and a work function of a gate electrode of the NMOS transistor primarily depends upon a material formed on the thin metal layer 54a. 
However, according to the above conventional method, the metal layer 54 is etched by a timed etching process, with which controlling uniformity of the thickness of the thin metal layer 54a is difficult. Thus, uniformity of the work function of the gate electrode of the NMOS transistor cannot be ensured.